IP Level Functional VerificationJOB DUTIES:Verification of a complex bridge IP using an equally complex SV/UVM verification environmentRegression debugDevelopment and analysis of functional coverageDevelopment of directed and random verification tests to validate IP/system functionDevelopment of verification components and toolsEXPERIENCE5 or more years of proven verification experience on large ASIC development projects in a hardware development setting.Strong background in System Verilog and UVM methodologies is a must.Strong debug skills and experience with debug tools such as Verdi.Proficient in Object Oriented programming, computer architecture and data structures.Knowledge of scripting languages, such as Perl or RubyStrong analytical/problem solving skills and pronounced attention to details.Strong interpersonal and communication skillsMust be comfortable working across geographies.Note :RemoteVIVA is an equal opportunity employer. All qualified applicants have an equal opportunity for placement, and all employees have an equal opportunity to develop on the job. This means that VIVA will not discriminate against any employee or qualified applicant on the basis of race, color, religion, sex, sexual orientation, gender identity, national origin, disability or protected veteran status.
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