Education: Bachelor’s Degree required? YesVerification Engineer for Memory ControllerSignificant UVM, SystemVerilog experience in complex test-benchesExperience working with DRAM controller, PHYs, memory models is preferredSignificant experience with general verification flows and metricsExcellent debug skillsWorking with big teams across multiple geographiesEXPERIENCE AND EDUCATION:7 or more years of proven verification experience on large ASIC development projects or software/firmware experience in a hardware development setting;Strong Verilog/SystemVerilog knowledgeHas developed or significantly changed components in UVM testbenches - monitors / checkers / sequencesSome experience with SVA or formal are preferred.Ability to debug design/TB failures using logfiles and waveformsKnowledge of scripting language (PYTHON or PERL)Strong analytical skills and attention to detail;Strong written and communication skills.Note :option to work remotely .VIVA is an equal opportunity employer. All qualified applicants have an equal opportunity for placement, and all employees have an equal opportunity to develop on the job. This means that VIVA will not discriminate against any employee or qualified applicant on the basis of race, color, religion, sex, sexual orientation, gender identity, national origin, disability or protected veteran status.
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