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Verification Engineer for Memory Controller

Reference Number: LSCAVE15111

Verification Engineer for Memory Controller
experience  Not Disclosed
location  Santa Clara, CA
duration  12.0 Months
salary  Not Disclosed
jobtype  Not Disclosed
Industry  Manufacturing
Job Description

Education: Bachelor’s Degree required? Yes

Verification Engineer for Memory Controller

Significant UVM, SystemVerilog experience in complex test-benches
Experience working with DRAM controller, PHYs, memory models is preferred
Significant experience with general verification flows and metrics
Excellent debug skills
Working with big teams across multiple geographies


7 or more years of proven verification experience on large ASIC development projects or software/firmware experience in a hardware development setting;
Strong Verilog/SystemVerilog knowledge
Has developed or significantly changed components in UVM testbenches - monitors / checkers / sequences
Some experience with SVA or formal are preferred.
Ability to debug design/TB failures using logfiles and waveforms
Knowledge of scripting language (PYTHON or PERL)
Strong analytical skills and attention to detail;
Strong written and communication skills.

Note :

option to work remotely .
VIVA is an equal opportunity employer. All qualified applicants have an equal opportunity for placement, and all employees have an equal opportunity to develop on the job. This means that VIVA will not discriminate against any employee or qualified applicant on the basis of race, color, religion, sex, sexual orientation, gender identity, national origin, disability or protected veteran status.

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