ASIC/RTL Design Engineer

ASIC/RTL Design Engineer

  Not Disclosed

  San Jose, CA

  12.0 Months

  Not Disclosed

  Not Disclosed

  Manufacturing

  $73.69/hour - $78.69/hour

Job Description

JOB DUTIES: The work will expose the designer to a number of IP including ARM cores, Ethernet, DDR, DMA, PCIE, SATA and client internal IP
s. Successful candidates will be responsible for leading, and participating in, the design of leading edge SoC
s in advanced digital CMOS processes. Our RTL Design Engineers are expected contribute in all aspects of SoC design including: Chip definition, Architecture development and modeling, Development of micro-architectural specifications, Conversion of micro-architectural specifications to logic implementation, Verification, emulation, debug, synthesis, and timing closure, Interfacing with physical execution, software, and silicon bring-up teams.

EXPERIENCE AND EDUCATION:
- SoC Architecture;
- Knowledge AND hand-on experience from industry ASIC design flow including RTL coding, IP Integration, debugging/verification, and supporting synthesis and timing closure.
- Working knowledge of ARM cores and other I/O standard interfaces.
- Roughly 10 years experience, but less is acceptable.
- Bachelors in electrical engineering or computer engineering is acceptable

An ideal candidate would also exhibit: Strong communication and documentation skills, Good organizational, time management and multitasking skills, Strong initiative and discipline to follow-through, Technical leadership


3 days onsite is required
VIVA is an equal opportunity employer. All qualified applicants have an equal opportunity for placement, and all employees have an equal opportunity to develop on the job. This means that VIVA will not discriminate against any employee or qualified applicant on the basis of race, color, religion, sex, sexual orientation, gender identity, national origin, disability or protected veteran status.