RTL Design Engineer

RTL Design Engineer

  Not Disclosed

  Santa Clara, CA

  12.0 Months

  Not Disclosed

  Not Disclosed

  Manufacturing

  $73.57/hour - $78.57/hour

Job Description

Looking for RTL design integration Engineer.

JOB DUTIES:

Responsible for RTL design using Verilog HDL for implementation and debug. Read and comprehend System on Chip level architectural specification. Write microarchitecture specification for new and modified functions. Responsible for linting and simulation of design. Work with synthesis and backend teams for physical implementation.

EDUCATION:

Bachelor's or Master's in Computer Engineering

KEY RESPONSIBILITIES:?
Perform RTL design of digital components in Verilog/systemverilog.
Analyze/fix Lint and CDC errors of the components.
Guarantee quality/timely deliverables meeting project’s schedule.
Help to improve/automate design process.

PREFERRED EXPERIENCE:

Knowledge of RISK-V processor integration Express
Multi-clock domain designs.
Design constraints for synthesis and static timing analysis.
Knowledge of AXI/AMBA protocol
Knowledge of front-end RTL design tools and methodologies.
Knowledge of scripting languages?like?Perl, tcl or cshell

Skills required:

RTL, System Verlog or Verilog, Understanding of How CPU sub systems will work.
Knowledge of RISK-V and Multi clock experience is plus.

Top Skills:

RTL.
SoC design integration.
AXI.
Lint/CDC.
RM CPU integration.

Note :

Onsite role .Open for hybrid role (3 days per week onsite).
7-8 experience is Minimum.
No travel required.
VIVA is an equal opportunity employer. All qualified applicants have an equal opportunity for placement, and all employees have an equal opportunity to develop on the job. This means that VIVA will not discriminate against any employee or qualified applicant on the basis of race, color, religion, sex, sexual orientation, gender identity, national origin, disability or protected veteran status.