Verification Engineer for Memory Controller• Significant UVM, SystemVerilog experience in complex test-benches• Experience working with DRAM controller, PHYs, memory models• Significant experience with general verification flows and metrics• Excellent debug skillsWorking with big teams across multiplegeographiesWorking with limited documentation - both for design and verificationEXPERIENCE AND EDUCATION:7 or more years of proven verification experience on large ASIC development projects or software/firmware experience in a hardware development setting;Strong Verilog/SystemVerilog knowledgeHas developed or significantly changed components in UVM testbenches - monitors / checkers / sequencesSome experience with SVAAbility to debug design/TB failures using logfiles and waveformsKnowledge of some scripting languageStrong analytical skills and attention to detail;Strong written and communication skillsVIVA is an equal opportunity employer. All qualified applicants have an equal opportunity for placement, and all employees have an equal opportunity to develop on the job. This means that VIVA will not discriminate against any employee or qualified applicant on the basis of race, color, religion, sex, sexual orientation, gender identity, national origin, disability or protected veteran status.
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