THE ROLE: Participate in the block-level functional verification of the transport layer of the Infinity Fabric interconnect.The Infinity Fabric is part of every new client product being developed across Client, Server, Graphics, and Semi-Custom markets. The transport layer of the interconnect is composed of the network of switches that move data within a given die paired with the external links that allow the fabric to be extended onto additional dies. THE PERSON The right candidate will have 10+ years experience verifying complex design blocks at the IP or SoC level using SystemVerilog/UVM or related technologies. The candidate will have a strong background in OOP, computer architecture, and data structures, and will have experience using debug tools such as Verdi.JOB DUTIES: Be part of a team of design and verification engineers, working closely with other team members to understand and verify the functionality of a given design element within the context of the block, chip and overall system. Be responsible for carefully documenting and executing test plan(s) consisting of directed and constrained-random tests to be run during simulation. Be expected to adopt the evolving verification methodologies used in the industry to functionally verify increasingly more complex designs within aggressive, market-driven schedules, and work within the existing verification infrastructure on currently active projects.VIVA is an equal opportunity employer. All qualified applicants have an equal opportunity for placement, and all employees have an equal opportunity to develop on the job. This means that VIVA will not discriminate against any employee or qualified applicant on the basis of race, color, religion, sex, sexual orientation, gender identity, national origin, disability or protected veteran status.
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