KEY RESPONSIBILITIES:Write micro-architecture documentation and own major portions of the design and implementation of blocks to meet functional, timing, area, and power requirements.Collaborate with architecture and hardware teams to understand the requirements.Work with verification and physical design teams to achieve high quality design and successful tape out.Design and implement logic functions that enable efficient test and debug.Participate in silicon bring-up for features owned.Contribute in cross-functional teams to solve novel problems across multiple functional areas in development of required features.Implement automation to increase design team efficiency.EXPERIENCE:Required:5-6+ years' experience requiredExperience in integrating ASIC IP into an SOC.Experience with synthesis, static timing analysis & optimizations.Nice-to-have:Experience writing timing constraints and exceptions.Experience with automation using scripting techniques such as PERL, Python or TclExperience in Power-saving techniques.Experience with Arm architecture and APB, AXI, CHI protocols.Experience with design involving Interconnects.Ability to develop clear and concise engineering documentation.Ability to organize and present complex technical information.Strong verbal and written communication skillsEDUCATION:Bachelor's degree requiredTop MUST HAVE skills:Experience in Designing RTL block for an SOC.Must have proven track record of ASIC design on several production tape-outs.Experience with Lint, CDC, RDC.Notes:100% onsite (4 days a week in office, Friday optional)
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