Description:Job Duties:Participate in the functional verification of a block(s) of complex ASICs and/or IP cores for an I/O SOC. Be part of a team of design verification team , working closely with other team members to understand and verify the functionality of a given design element within the context of the block, chip and overall system. Candidate will be participating in the UVM testbench development, test plan & verification of a Complex SOCResponsibilities:Create and implement a verification plan.Develop and execute test cases to ensure the functionality, performance, and reliability of the chip design.Collaborate with the hardware design team to identify and resolve issues.Work in a UVM environment.Use of Assertions, and randomized and direct tests.Code coverage and debugging.Analyze and report on verification results.Qualifications:BSEE or CS10-15 years of solid experience in UVM design verificationStrong knowledge of UVM verification, DV tools & methodologiesDeep technical background in AISC & SOC verification.Experience with CPUs & high speed I/OsExperience with Cadence or Synopsys Verification tools & VerdiSolid experience in System VerilogNotes:Must be able to come onsite 3 days per week VIVA is an equal opportunity employer. All qualified applicants have an equal opportunity for placement, and all employees have an equal opportunity to develop on the job. This means that VIVA will not discriminate against any employee or qualified applicant on the basis of race, color, religion, sex, sexual orientation, gender identity, national origin, disability or protected veteran status
Description:Job Duties:Participate in the functional verification of a block(s) of complex ASICs and/or IP cores for an I/O SOC. Be part of a team of design verification team , working closely with other team members to understand and verify the functionality of a given design element within the context of the block, chip and overall system. Candidate will be participating in the UVM testbench development, test plan & verification of a Complex SOCResponsibilities:Create and implement a verification plan.Develop and execute test cases to ensure the functionality, performance, and reliability of the chip design.Collaborate with the hardware design team to identify and resolve issues.Work in a UVM environment.Use of Assertions, and randomized and direct tests.Code coverage and debugging.Analyze and report on verification results.Qualifications:BSEE or CS10-15 years of solid experience in UVM design verificationStrong knowledge of UVM verification, DV tools & methodologiesDeep technical background in AISC & SOC verification.Experience with CPUs & high speed I/OsExperience with Cadence or Synopsys Verification tools & VerdiSolid experience in System VerilogNotes:Must be able to come onsite 3 days per week
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