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Design Verification Engineer


Reference Number: GDCAAD1

Design Verification Engineer
experience  Not Disclosed
location  Santa Clara, CA
duration  12.0 Months
salary  Not Disclosed
jobtype  Not Disclosed
Industry  Manufacturing
duration  $81.01/hour - $86.01/hour
Job Description

Description:

THE ROLE:

  • We are looking for an adaptive, self-motivative Design Verification Engineer to join our growing team. As a key contributor, you will be part of a leading team to drive and improve client's abilities to deliver the highest quality, industry-leading technologies to market. Be a part of a team that delivers Industry leading IP and help our experts in RTL, FW, circuit, and architecture teams develop leading edge and differentiating IPs.

THE PERSON:

  • You have a passion for modern, complex processor architecture, digital design, and verification in general. You are a team player who has excellent communication skills and experience collaborating with other engineers located in different sites/time zones. You have strong analytical and problem-solving skills and are willing to learn and ready to take on problems.

KEY RESPONSIBILITIES:

  • Develop/Maintain tests for functional verification.
  • Build the directed and random verification tests, debug test failures to determine the root cause, work with RTL and firmware engineers to resolve design defects and correct any test issues.
  • Work on functional & code coverage verification.
  • Provide technical support to other teams

PREFERRED EXPERIENCE:

  • Experience with C/C++
  • Experience with Verilog, System Verilog, and modern verification libraries like UVM
  • 10+years of ASIC design verification experience
  • Experience / Background with DDR or Memory Controller. PHY Verification is a plus
  • Experience with scripting languages like Python, Perl and TCL is a plus.
  • Collaborate with architects, hardware engineers, and firmware engineers to understand the new features to be verified
  • Understanding of Design for Test methodologies and DFT verification experience is a plus
  • Proficient in debugging firmware and RTL code using simulation tools

ACADEMIC CREDENTIALS:

  • Bachelor’s or master’s degree in computer engineering/Electrical Engineering

VIVA is an equal opportunity employer. All qualified applicants have an equal opportunity for placement, and all employees have an equal opportunity to develop on the job. This means that VIVA will not discriminate against any employee or qualified applicant on the basis of race, color, religion, sex, sexual orientation, gender identity, national origin, disability or protected veteran status

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