Description:The Role:The Memory IO team is looking for a passionate and experienced Firmware designers for the pre/post-silicon development of high-speed LPDDR, DDR and inter-chip IO IPs. Be a part of the definition, design and development and productization phase of industry-leading Memory PHYs and interface IP. This opportunity includes enabling of new PHY designs at the microarchitecture, firmware/hardware co-design, and algorithm design level.Be a part of a team that delivers Industry leading IP and help our experts in RTL, FW, circuit and architecture teams develop leading edge Memory interfaces.The Person:Will have strong analytical/problem-solving skills and pronounced attention to details. Must be a self-starter, and able to independently drive tasks to completion. Will have strong interpersonal and communication skillsRESPONSIBILITIES:Firmware design and development of DDR PHY & DRAM Training stepsFirmware development of DDR PHY for ATE Testing, IP Char & SoC PowerPre-silicon FW coding and simulation against Architectural and RTL modelsPost-silicon lab bring-up and optimization of DDR Init and Run Time FWPost-silicon DDR Training enhancements to enable robust links for higher reliability / higher frequency marginWorking with SoC/Product firmware teams to define features and specsPreference & Skill Sets :+5 years’ experience as firmware engineer.Excellent knowledge of C, C++ and any scripting language, such as Python.Good Knowledge of Verilog/SystemVerilog and digital simulation debug.Ability to adapt learn new toolsets and frameworks is required.Strong understanding of synchronization techniques (handshakes, message passing); knowledge of hardware level clocking and synchronization is a plusPost-silicon experience developing firmware on real hardware is required. Experience with SERDES, DDR, Memory Controller Design experience is preferredStrong understanding of computer organization/architecture.Laboratory experience, including the use of equipment: oscilloscopes, logic analyzers, etc.Experience with low level, physical phenomena-oriented logic design is an asset (dealing with IO, clocking, voltage control, etc.)EDUCATION:Bachelor’s degree in electrical or computer engineering is strongly desired. Master's or PhD degree is a plus. VIVA is an equal opportunity employer. All qualified applicants have an equal opportunity for placement, and all employees have an equal opportunity to develop on the job. This means that VIVA will not discriminate against any employee or qualified applicant on the basis of race, color, religion, sex, sexual orientation, gender identity, national origin, disability or protected veteran status
Description:The Role:The Memory IO team is looking for a passionate and experienced Firmware designers for the pre/post-silicon development of high-speed LPDDR, DDR and inter-chip IO IPs. Be a part of the definition, design and development and productization phase of industry-leading Memory PHYs and interface IP. This opportunity includes enabling of new PHY designs at the microarchitecture, firmware/hardware co-design, and algorithm design level.Be a part of a team that delivers Industry leading IP and help our experts in RTL, FW, circuit and architecture teams develop leading edge Memory interfaces.The Person:Will have strong analytical/problem-solving skills and pronounced attention to details. Must be a self-starter, and able to independently drive tasks to completion. Will have strong interpersonal and communication skillsRESPONSIBILITIES:Firmware design and development of DDR PHY & DRAM Training stepsFirmware development of DDR PHY for ATE Testing, IP Char & SoC PowerPre-silicon FW coding and simulation against Architectural and RTL modelsPost-silicon lab bring-up and optimization of DDR Init and Run Time FWPost-silicon DDR Training enhancements to enable robust links for higher reliability / higher frequency marginWorking with SoC/Product firmware teams to define features and specsPreference & Skill Sets :+5 years’ experience as firmware engineer.Excellent knowledge of C, C++ and any scripting language, such as Python.Good Knowledge of Verilog/SystemVerilog and digital simulation debug.Ability to adapt learn new toolsets and frameworks is required.Strong understanding of synchronization techniques (handshakes, message passing); knowledge of hardware level clocking and synchronization is a plusPost-silicon experience developing firmware on real hardware is required. Experience with SERDES, DDR, Memory Controller Design experience is preferredStrong understanding of computer organization/architecture.Laboratory experience, including the use of equipment: oscilloscopes, logic analyzers, etc.Experience with low level, physical phenomena-oriented logic design is an asset (dealing with IO, clocking, voltage control, etc.)EDUCATION:Bachelor’s degree in electrical or computer engineering is strongly desired. Master's or PhD degree is a plus.
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