Hybrid Role in San Jose, CADescription:Mixed Signal Model Verification EngineerWe are seeking a detail-oriented mixed signal model engineer to verify behavioral models written in SystemVerilog, both logic and real number. It will involve writing constraints and stimulus for CAD tools to run equivalence check against the schematic. It is required to read and understand the mixed signal circuit schematic to debug any mismatch between behavioral model and circuit transistor-level behavior. Modification to the behavioral models to make it equivalent to the mixed signal circuit is expected.MUST HAVE SKILLS:Extensive experience in modeling mixed signal circuits in SystemVerilog, including real number modelingStrong understanding of HDL/SPICE co-simulationsStrong understanding of custom circuit schematicStrong background in analog integrated circuit designProficiency in RTL design languages like SystemVerilogExperience with formal equivalence checking tools like ESPNotes:HybridVIVA is an equal opportunity employer. All qualified applicants have an equal opportunity for placement, and all employees have an equal opportunity to develop on the job. This means that VIVA will not discriminate against any employee or qualified applicant on the basis of race, color, religion, sex, sexual orientation, gender identity, national origin, disability or protected veteran status
Description:Mixed Signal Model Verification EngineerWe are seeking a detail-oriented mixed signal model engineer to verify behavioral models written in SystemVerilog, both logic and real number. It will involve writing constraints and stimulus for CAD tools to run equivalence check against the schematic. It is required to read and understand the mixed signal circuit schematic to debug any mismatch between behavioral model and circuit transistor-level behavior. Modification to the behavioral models to make it equivalent to the mixed signal circuit is expected.MUST HAVE SKILLS:Extensive experience in modeling mixed signal circuits in SystemVerilog, including real number modelingStrong understanding of HDL/SPICE co-simulationsStrong understanding of custom circuit schematicStrong background in analog integrated circuit designProficiency in RTL design languages like SystemVerilogExperience with formal equivalence checking tools like ESPNotes:Hybrid
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