Description:JOB DUTIES:Develop, enhance, and maintain SystemC/TLM2 models for memory controllers, peripherals, and interconnects, ensuring they accurately simulate the behavior and performance characteristics of the hardware.Collaborate with cross teams to integrate models into client tools used for system-level designs, ensuring proper functionality and performance.Identify bottlenecks and performance issues within models and work to optimize their performance to meet design specifications.Develop and execute testbenches to validate the functionality and correctness of models, as well as participate in system-level testing and debugging.Create clear and comprehensive documentation for models, including usage guidelines and design specifications.Deliverables:Cycle approximate performance modelsSV/UVM Functional and Performance VerificationEXPERIENCE AND EDUCATION:5 or more years of proven modeling & verification experience on large ASIC development projects or software/firmware experience in a hardware development setting; Strong background in C/C++ development in a Linux Environment; Strong debug skills and experience with debug tools such as Gdb, Valgrind ;Knowledge of Perl and Makefiles; Experience in Verilog/SystemVerilog/SystemC, preferred; Experience in C/Verilog environment using DPI/PLI, preferred; Strong analytical skills and attention to detail; Excellent written and communication skills; PCIe & AXI Knowledge Preferred VIVA is an equal opportunity employer. All qualified applicants have an equal opportunity for placement, and all employees have an equal opportunity to develop on the job. This means that VIVA will not discriminate against any employee or qualified applicant on the basis of race, color, religion, sex, sexual orientation, gender identity, national origin, disability or protected veteran status
Description:JOB DUTIES:Develop, enhance, and maintain SystemC/TLM2 models for memory controllers, peripherals, and interconnects, ensuring they accurately simulate the behavior and performance characteristics of the hardware.Collaborate with cross teams to integrate models into client tools used for system-level designs, ensuring proper functionality and performance.Identify bottlenecks and performance issues within models and work to optimize their performance to meet design specifications.Develop and execute testbenches to validate the functionality and correctness of models, as well as participate in system-level testing and debugging.Create clear and comprehensive documentation for models, including usage guidelines and design specifications.Deliverables:Cycle approximate performance modelsSV/UVM Functional and Performance VerificationEXPERIENCE AND EDUCATION:5 or more years of proven modeling & verification experience on large ASIC development projects or software/firmware experience in a hardware development setting; Strong background in C/C++ development in a Linux Environment; Strong debug skills and experience with debug tools such as Gdb, Valgrind ;Knowledge of Perl and Makefiles; Experience in Verilog/SystemVerilog/SystemC, preferred; Experience in C/Verilog environment using DPI/PLI, preferred; Strong analytical skills and attention to detail; Excellent written and communication skills; PCIe & AXI Knowledge Preferred
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