RemoteDescription:JOB DUTIES:Develop, enhance, and maintain SystemC/TLM2 models for memory controllers, peripherals, and interconnects, ensuring they accurately simulate the behavior and performance characteristics of the hardware.Collaborate with cross teams to integrate models into the client tools used for system-level designs, ensuring proper functionality and performance.Identify bottlenecks and performance issues within models and work to optimize their performance to meet design specifications.Develop and execute testbenches to validate the functionality and correctness of models, as well as participate in system-level testing and debugging.Create clear and comprehensive documentation for models, including usage guidelines and design specifications.Deliverables:Cycle approximate performance modelsSV/UVM Functional and Performance VerificationEXPERIENCE AND EDUCATION:B.E/M.E/M.Tech or B.S/M.S in EE/CSE with over 5 years of recent hands-on experience in SystemC and TLM2 modelingProficiency in C/C++ programming.Understanding of memory controller architectures, including DDR, LPDDR, and other relevant standards is preferred.UVM verification experience is preferred.Experience with debuggers and handling complex projects.Experience working in geographically dispersed teams; must be a strong team player.Knowledge of system-level architecture including buses like AXI/AHB and bridges is a plus.Familiarity with version control systems such as Perforce or Git.Minimum 5 years of experience in SystemC.Recent and relevant experience with SystemC.Hands-on modeling projects using SystemC.Familiarity with Transaction-Level Modeling (TLM) concepts and implementation.Experience in performance modeling and architecture exploration using SystemC.Ability to work with C++ integration, since SystemC is built on C++.Exposure to verification methodologies in SystemC (e.g., testbench creation, simulation).Knowledge of modeling at different abstraction levels (e.g., behavioral, RTL, TLM).Notes:Preference is Hybrid but Open to a fully remote candidate.VIVA is an equal opportunity employer. All qualified applicants have an equal opportunity for placement, and all employees have an equal opportunity to develop on the job. This means that VIVA will not discriminate against any employee or qualified applicant on the basis of race, color, religion, sex, sexual orientation, gender identity, national origin, disability or protected veteran status
Description:
JOB DUTIES:Develop, enhance, and maintain SystemC/TLM2 models for memory controllers, peripherals, and interconnects, ensuring they accurately simulate the behavior and performance characteristics of the hardware.Collaborate with cross teams to integrate models into the client tools used for system-level designs, ensuring proper functionality and performance.Identify bottlenecks and performance issues within models and work to optimize their performance to meet design specifications.Develop and execute testbenches to validate the functionality and correctness of models, as well as participate in system-level testing and debugging.Create clear and comprehensive documentation for models, including usage guidelines and design specifications.Deliverables:Cycle approximate performance modelsSV/UVM Functional and Performance VerificationEXPERIENCE AND EDUCATION:B.E/M.E/M.Tech or B.S/M.S in EE/CSE with over 5 years of recent hands-on experience in SystemC and TLM2 modelingProficiency in C/C++ programming.Understanding of memory controller architectures, including DDR, LPDDR, and other relevant standards is preferred.UVM verification experience is preferred.Experience with debuggers and handling complex projects.Experience working in geographically dispersed teams; must be a strong team player.Knowledge of system-level architecture including buses like AXI/AHB and bridges is a plus.Familiarity with version control systems such as Perforce or Git.Minimum 5 years of experience in SystemC.Recent and relevant experience with SystemC.Hands-on modeling projects using SystemC.Familiarity with Transaction-Level Modeling (TLM) concepts and implementation.Experience in performance modeling and architecture exploration using SystemC.Ability to work with C++ integration, since SystemC is built on C++.Exposure to verification methodologies in SystemC (e.g., testbench creation, simulation).Knowledge of modeling at different abstraction levels (e.g., behavioral, RTL, TLM).
Notes:
Preference is Hybrid but Open to a fully remote candidate.
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