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Power Optimization Engineer


Reference Number: GDCASP23

Power Optimization Engineer
experience  Not Disclosed
location  San Jose, CA
duration  3.0 Months
salary  Not Disclosed
jobtype  Not Disclosed
Industry  Manufacturing
duration  $120.89/hour - $125.89/hour
Job Description

Hybrid Role in San Jose, CA

Description:

We are seeking a power optimization engineer who has expertise in power optimization methodology to analyze and optimize pre-silicon IP RTL designs.

Key responsibilities:
Implement the flow and methodology at the IP-level to align with the internal power optimization workflow for RTL power optimization
Automate power data collection and track key power metrics through the development phases
Support RTL and gate-level power rollup and analysis
Work closely with design and implementation teams to analyze power data and identify power optimization opportunities

TOP MUST HAVE SKILLS:
1) Extensive power optimization experience in low power ASIC design
2) Proficiency in RTL design languages like Verilog or VHDL
3) Proficiency in programming languages like Perl, Python, and/or Ruby
4) Experience with power analysis tools like PowerArtist, PrimePower RTL and/or PrimeTime PX

Notes:
Hybrid


VIVA is an equal opportunity employer. All qualified applicants have an equal opportunity for placement, and all employees have an equal opportunity to develop on the job. This means that VIVA will not discriminate against any employee or qualified applicant on the basis of race, color, religion, sex, sexual orientation, gender identity, national origin, disability or protected veteran status

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