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RTL Design Engineer


Reference Number: GDCARD69

RTL Design Engineer
experience  Not Disclosed
location  Santa Clara, CA (100% Remote)
duration  12 Months
salary  Not Disclosed
jobtype  Not Disclosed
Industry  Manufacturing
duration  $-4/hour - $1/hour
Job Description

Hybrid or remote options ; Candidate can work out of other client's Locations

Description:

JOB DUTIES:

Responsible for RTL design using Verilog HDL for implementation and debug. Read and comprehend Analog Macro level architectural specification.

RTL Candidate Requirements

Top 3 skills:

Modelling Analog-Mixed signal circuits in RTL, with experience in LDOs, BGs and EMC
Ability to run and debug LECC for design
Run quality check tool such as Spyglass Lint and fix issues.

Ability to provide direction on optimal/efficient hierarchical design of Analog-Mixed signal designs
Ability to run Co-Sim preferred
Ability to debug DV issues preferred

Experience:

7+ years' experience required

Education:

Bachelor's (required) or Master's in Computer Engineering

Notes:

Hybrid or remote options ; Candidate can work out of other client's Locations


VIVA is an equal opportunity employer. All qualified applicants have an equal opportunity for placement, and all employees have an equal opportunity to develop on the job. This means that VIVA will not discriminate against any employee or qualified applicant on the basis of race, color, religion, sex, sexual orientation, gender identity, national origin, disability or protected veteran status

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