Hybrid or remote options ; Candidate can work out of other client's LocationsDescription:JOB DUTIES:Responsible for RTL design using Verilog HDL for implementation and debug. Read and comprehend Analog Macro level architectural specification.RTL Candidate RequirementsTop 3 skills:Modelling Analog-Mixed signal circuits in RTL, with experience in LDOs, BGs and EMCAbility to run and debug LECC for designRun quality check tool such as Spyglass Lint and fix issues.Ability to provide direction on optimal/efficient hierarchical design of Analog-Mixed signal designsAbility to run Co-Sim preferredAbility to debug DV issues preferredExperience:7+ years' experience requiredEducation:Bachelor's (required) or Master's in Computer EngineeringNotes:Hybrid or remote options ; Candidate can work out of other client's LocationsVIVA is an equal opportunity employer. All qualified applicants have an equal opportunity for placement, and all employees have an equal opportunity to develop on the job. This means that VIVA will not discriminate against any employee or qualified applicant on the basis of race, color, religion, sex, sexual orientation, gender identity, national origin, disability or protected veteran status
Description:JOB DUTIES:Responsible for RTL design using Verilog HDL for implementation and debug. Read and comprehend Analog Macro level architectural specification.RTL Candidate RequirementsTop 3 skills:Modelling Analog-Mixed signal circuits in RTL, with experience in LDOs, BGs and EMCAbility to run and debug LECC for designRun quality check tool such as Spyglass Lint and fix issues.Ability to provide direction on optimal/efficient hierarchical design of Analog-Mixed signal designsAbility to run Co-Sim preferredAbility to debug DV issues preferredExperience:7+ years' experience requiredEducation:Bachelor's (required) or Master's in Computer EngineeringNotes:Hybrid or remote options ; Candidate can work out of other client's Locations
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