Hybrid Work Environment (As of now), 3 days in Office (Tue, Wed, Thu)Description:We are looking for someone with close to 3-5 years of experience in hardware design.We are looking for to fill as Emulation and Prototyping Engineer. Key skill would be hands on experience with Synopsys HAPS, Zebu, Protium, Palladium, or other FPGA/emulation platforms.Must have skills:- FPGA Design Experience- RTL Design using Verilog/System Verilog- Exposure to any Emulation or Prototyping Platform (HAPS/Zebu, Protium/Palladium)JOB DUTIES:In this position, the engineer will have the following key responsibilities: Hardware emulation model creation. Importing design RTL. Provide RTL patches to address non-synthesis issues. Compile emulation model. Debugging issues found during the process, bring-up, validation, and production phases of SOC programs. Perform pre-silicon verification & validation and emulation to ensure functional correctness and performance. Partition large SoC RTL for multi-FPGA platforms; develop and maintain HAPS/FPGA build infrastructure including scripts, flows, and makefiles. Integrate custom transactors, high-speed interfaces, and debug instrumentation. Work with various pre-silicon tools and concepts such as emulation, FPGA, software models, N-1 silicon usage, etc., including pre-to-post-silicon initiativesEXPERIENCE AND EDUCATION:3-4 years of experience on emulation based functional and performance verification for multimillion gate SoC designs. Should have strong exposure to RTL coding and SOC bring-up. Hands-on experience with Synopsys HAPS, Protium, Palladium, or other FPGA/emulation platforms. Experience with SoC buses and protocols: AXI, ACE, APB, PCIe, DDR, Ethernet, SerDes-based links, etc. Strong RTL design background using SystemVerilog/Verilog. Good debugging skills, experience of working with various debugging tools on RTL like Verdi, fsdb analysis. Familiarity with ASIC design flows including emulation, verification and bring up. Expertise in scripting/automation: Python, Perl, Tcl, Make/CMake, Shell.Notes:Hybrid Work Environment (As of now), 3 days in Office (Tue, Wed, Thu)VIVA is an equal opportunity employer. All qualified applicants have an equal opportunity for placement, and all employees have an equal opportunity to develop on the job. This means that VIVA will not discriminate against any employee or qualified applicant on the basis of race, color, religion, sex, sexual orientation, gender identity, national origin, disability or protected veteran status
Description:We are looking for someone with close to 3-5 years of experience in hardware design.We are looking for to fill as Emulation and Prototyping Engineer. Key skill would be hands on experience with Synopsys HAPS, Zebu, Protium, Palladium, or other FPGA/emulation platforms.Must have skills:- FPGA Design Experience- RTL Design using Verilog/System Verilog- Exposure to any Emulation or Prototyping Platform (HAPS/Zebu, Protium/Palladium)JOB DUTIES:In this position, the engineer will have the following key responsibilities: Hardware emulation model creation. Importing design RTL. Provide RTL patches to address non-synthesis issues. Compile emulation model. Debugging issues found during the process, bring-up, validation, and production phases of SOC programs. Perform pre-silicon verification & validation and emulation to ensure functional correctness and performance. Partition large SoC RTL for multi-FPGA platforms; develop and maintain HAPS/FPGA build infrastructure including scripts, flows, and makefiles. Integrate custom transactors, high-speed interfaces, and debug instrumentation. Work with various pre-silicon tools and concepts such as emulation, FPGA, software models, N-1 silicon usage, etc., including pre-to-post-silicon initiativesEXPERIENCE AND EDUCATION:3-4 years of experience on emulation based functional and performance verification for multimillion gate SoC designs. Should have strong exposure to RTL coding and SOC bring-up. Hands-on experience with Synopsys HAPS, Protium, Palladium, or other FPGA/emulation platforms. Experience with SoC buses and protocols: AXI, ACE, APB, PCIe, DDR, Ethernet, SerDes-based links, etc. Strong RTL design background using SystemVerilog/Verilog. Good debugging skills, experience of working with various debugging tools on RTL like Verdi, fsdb analysis. Familiarity with ASIC design flows including emulation, verification and bring up. Expertise in scripting/automation: Python, Perl, Tcl, Make/CMake, Shell.Notes:Hybrid Work Environment (As of now), 3 days in Office (Tue, Wed, Thu)
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