Job Description:Jr Memory Systems EngineerJOB DUTIES:In this role, this engineer will be part of a highly technical team that develops test plans, completes functional & electrical validation, & debugs issues for new processor silicon interface features with strong focus on power management. Writes comprehensive electrical & functional test plans for the processor interface validation of processors. Executes electrical & functional test plans for client processors using hardware & software validation tools, oscilloscopes, & logic analyzers. Debug of electrical & functional issues for new processors. Provides detailed input into the platform definition & review of platform designs used in the silicon validation of new processors. Provides technical guidance and training to less experienced engineers and technicians in the planning, test, & debug processor validation.EXPERIENCE AND EDUCATION:Bachelors in Electrical Engineering or Computer Engineering with 0-2 years of related experience;or Masters plus at least 2 years directly related experience (an advanced degree will be considered a plus);Requires experience and demonstrated technical expertise in the development & execution of platform level electrical & functional test plans;Platform level electrical characterization experience with processor I/O interfaces is considered, preferred;Requires experience and demonstrated technical expertise in the debug of processor & PC platform I/O interfaces.Demonstrated experience with or knowledge using oscilloscopes, reading schematics and layout documentation, and MS Windows and Office applications;Requires good written and oral communication skills;Demonstrate the ability to communicate with a variety of engineering disciplines and management.Responsibilities:Execute electrical, functional, & system tests of DDR5 and LPDDR5x memory sub-system test plans as part of a post silicon platform engineering team using hardware and software validation tools, oscilloscopes, and logic analyzers.Develop technical test plans and tools to support platform level silicon bring-up and the validation execution of DDR5 and LPDDR5x memory subsystem.Analyze & debug electrical and functional test data to drive into production SOC and system solution decisions.Supports lab functions including rework, inventory, & system test of platformsSkills required:BS-EE / BS-CE / Masters + t 1 years directly related experience.Demonstrated expertise in the development and execution of platform level memory interface electrical and functional test plansKnowledge of PC architectures and system technologies.Demonstrated experience using oscilloscopeGood written and oral communication skills VIVA is an equal opportunity employer. All qualified applicants have an equal opportunity for placement, and all employees have an equal opportunity to develop on the job. This means that VIVA will not discriminate against any employee or qualified applicant on the basis of race, color, religion, sex, sexual orientation, gender identity, national origin, disability or protected veteran status
Job Description:Jr Memory Systems EngineerJOB DUTIES:In this role, this engineer will be part of a highly technical team that develops test plans, completes functional & electrical validation, & debugs issues for new processor silicon interface features with strong focus on power management. Writes comprehensive electrical & functional test plans for the processor interface validation of processors. Executes electrical & functional test plans for client processors using hardware & software validation tools, oscilloscopes, & logic analyzers. Debug of electrical & functional issues for new processors. Provides detailed input into the platform definition & review of platform designs used in the silicon validation of new processors. Provides technical guidance and training to less experienced engineers and technicians in the planning, test, & debug processor validation.EXPERIENCE AND EDUCATION:Bachelors in Electrical Engineering or Computer Engineering with 0-2 years of related experience;or Masters plus at least 2 years directly related experience (an advanced degree will be considered a plus);Requires experience and demonstrated technical expertise in the development & execution of platform level electrical & functional test plans;Platform level electrical characterization experience with processor I/O interfaces is considered, preferred;Requires experience and demonstrated technical expertise in the debug of processor & PC platform I/O interfaces.Demonstrated experience with or knowledge using oscilloscopes, reading schematics and layout documentation, and MS Windows and Office applications;Requires good written and oral communication skills;Demonstrate the ability to communicate with a variety of engineering disciplines and management.Responsibilities:Execute electrical, functional, & system tests of DDR5 and LPDDR5x memory sub-system test plans as part of a post silicon platform engineering team using hardware and software validation tools, oscilloscopes, and logic analyzers.Develop technical test plans and tools to support platform level silicon bring-up and the validation execution of DDR5 and LPDDR5x memory subsystem.Analyze & debug electrical and functional test data to drive into production SOC and system solution decisions.Supports lab functions including rework, inventory, & system test of platformsSkills required:BS-EE / BS-CE / Masters + t 1 years directly related experience.Demonstrated expertise in the development and execution of platform level memory interface electrical and functional test plansKnowledge of PC architectures and system technologies.Demonstrated experience using oscilloscopeGood written and oral communication skills
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